The present invention relates generally to design automation, and relates more particularly to at-speed testing of integrated circuit chips.
When integrated circuit (IC) chips come off the manufacturing line, the chips are tested “at-speed” to ensure that they perform correctly (and to filter out chips that do not perform correctly). In particular, a set of paths is selected, and the set of paths is then tested for each chip in order to identify the chips in which one or more of the selected paths fail timing requirements. Selection of these paths is complicated by the presence of process variations. Because of these variations, different paths can be critical in different chips. That is, a path that is critical in one chip may not be critical in another chip, and vice versa. Some paths do have a higher probability of being critical, but conventional testing methodologies fail to identify the paths that are statistically most likely to fail, taking into account process variations for the entire process space.
Thus, there is a need in the art for a method and apparatus for statistical path selection for at-speed testing.